The present invention relates to a semiconductor device and, more particularly, to metal-oxide-silicon (MOS) and metal-insulator-silicon (MIS) semiconductor devices having an LDD (lightly doped drain) structure and a method of manufacturing such a semiconductor device.
The structure of a conventional MOS semiconductor device and the contact portion thereof are shown in FIGS. 1 and 2, respectively. and the manufacturing process for a semiconductor device having an LDD structure is shown in FIGS. 3(a) to 3(e).
In these drawings, the MOS semiconductor device depicted includes a silicon (Si) substrate 1 having a surface-adjacent diffusion layer 2 formed therein. The layer 2 constitutes a source region or a drain region. The diffusion layer 2 is formed to a low-concentration region 2a and a high-concentration region 2b. Overlying the substrate 1 is a gate insulating film 4 and thereabove a gate electrode 3. Also depicted are an interlayer insulating film 10 which generally overcovers the components lying thereunder, namely side wall 6 and a first wiring layer 7 (FIG. 2), the gate electrode 3, and the underlying gate insulating film 4. A second wiring layer 8 overlies the interlayer insulating film 5; the second wiring layer 8, through an opening 9 in the interlayer insulating film 10, penetrates to and contacts the major surface of the semiconductor substrate 1 at the diffusion layer region 2 thereof. The side wall 6 is formed on either side of gate electrode 3 on gate insulating film 4. The gate insulating film 4 is supported on the substrate 1 in such manner that the gate electrode 3 overspans diffusion layers 2.
By an LDD structure, generally speaking, is meant a structure in which the diffusion layer 2 is composed of a region 2a having a low concentration and a region 2b having a high concentration, as shown in FIG. 1. The low concentration of the region 2a prevents the diffusion layer 2 from extending to the region in which a channel is to be formed, namely, to the portion under the gate insulating film 4, thereby definitively establishing the channel length.
The LDD structure, in which the region 2a increases the resistance of the portion under the gate insulating film 4, relaxes the electric field produced in the vicinity of the drain, thereby suppressing the deterioration of the characteristics of the metal insulator semiconductor field effect transistor (hereinunder referred to as "MISFET"). Specifically, a certain fluctuation in threshold value is suppressed. That fluctuation occurs when carriers are injected and captured in the gate insulating film 4; in their words, the so-called hot carrier phenomenon is suppressed. A conventional manufacturing process for a semiconductor device having a LDD structure will now be described with reference to FIGS. 3(a) to 3(e).
As shown in FIG. 3(a), a gate insulating film layer 4 is first formed on the substrate 1 by a conventional method. Then the gate electrode 3 is formed on the gate insulating film 4 by a conventional method. The diffusion layer 2a having a low concentration is next formed, as shown in FIG. 3(b). Then, as shown in FIG. 3(c), the interlayer insulating film 6a is formed. The side wall 6 is to be defined from the interlayer insulating film 6a. Next, as shown in FIG. 3(d), the side wall 6 is formed by anisotropic etching of the interlayer insulating film 6a. Finally, the diffusion layer 2b having a high concentration is formed, as shown in FIG. 3(e).
Such an LDD structure increases, and in this sense improves, the breakdown voltage which the semiconductor structure should withstand. Another advantageous effect is reduction in the above discussed fluctuation of the threshold value. The reduction is significant, so that the reliability of the transistor is greatly improved.
Japanese Patent Laid-Open No. 68776 (1976) discloses a MISFET having one conductivity type of source region and drain region formed on a semiconductor substrate of the opposite conductivity type. The drain region consists of a central portion having a high surface impurity concentration, and of a low impurity concentration portion which surrounds the central portion. That is, this MISFET adopts a double drain structure in order to relax the electric field produced in the vicinity of the drain region and to prevent the fluctuation of the threshold value due to the hot carrier phenomenon.
Japanese Patent Laid-Open No. 194568 (1985) discloses an integrated circuit (IC) provided with a MISFET which is capable of definitively establishing the effective channel length of the MISFET, thereby preventing the so-called short channel effect. In this manner, the degree of integration of the IC is improved, and the speed of the operation time is increased. For these purposes, the IC is composed of a semiconductor substrate which contains the impurities for constituting the drain region and the source region, respectively. These regions consist of two semiconductor regions of the same conductivity type but having different impurity densities. The impurities are introduced through the gate electrode and the side wall provided on both sides thereof as a mask. This prevents extension of the source region or the drain region to that region in which a channel is to be formed thus and definitively establishes the effective channel length.
Japanese Patent Laid-Open No. 20369 (1986) discloses a method of forming an LDD type semiconductor device. This method comprises the following steps. A gate insulating film is formed on a semiconductor substrate surrounded by a device isolation device region, and a gate electrode is formed on the gate insulating film. Then there is formed a first impurity layer of the second conductivity type by introducing impurities to the substrate while using the gate electrode as a mask. An insulating film is deposited on the entire surface; portions of the insulating film are removed by reactive ion etching but in such a manner as to retain the film on the side surface of the gate electrode and in the vicinity thereof. A second impurity layer of the second conductivity type is formed by introducing impurities to the substrate while using the gate electrode and the remaining insulating film as a mask so as to form source and drain regions. A mask material layer is formed so as to have a selective etching property with respect to the insulating film on the entire surface. The mask material layer is selectively removed until a part of the remaining insulating film on the side surface of the gate electrode is exposed. The remaining insulating film is selectively removed by using the remaining mask material layer so as to form a gap portion between the insulating film and the gate electrode. Impurities are introduced to the substrate from the gap so as to form a third impurity layer of the first conductivity type (e.g. a P.sup.- type layer).
The purpose for partially forming the third impurity layer of the first conductivity type is to suppress an extension of the depletion layer. That extension would otherwise be induced by the drain voltage in that region of the substrate which is of the first conductivity type and is in the vicinity of the side wall of the gate electrode As a result the contact portion of the P.sup.- type layer which contains the source and drain regions is reduced in comparison with still earlier prior art.
The above-described conventional MOS semiconductor devices, however, have the following problems and shortcomings.
(1) As shown in FIG. 2, the contact portion between the wiring layer 8 and diffusion layer 2 constitutes a hole-like opening portion of length l. Typically in the prior art, an alignment allowance a for photolithography is necessary in order to prevent short circuiting of the first wiring layer 7 and the second wiring layer 8 through the opening portion 9. Since the alignment allowance a is determined by the performance of an exposing device, it cannot be simply reduced. Thus, this is an obstacle to large scale integration.
(2) For a similar reason to that of (1), the alignment allowance a adds to the length of the second wiring layer 8; the additional length introduces resistance which delays propagation and makes speed-up of the operation well-nigh impossible.
(3) For a similar reason to that of (1), the alignment allowance a adds to the parasitic diffusion capacitance, thereby making speed-up of the operation well-nigh impossible.
Accordingly, there is a need to speed-up the operation of the semiconductor device by reducing wiring layer resistances and parasitic diffusion capacitance, and to provide manufacturing methods which will assure achievement of such reductions in resistance and capacitance. Further, it is required to render the IC chip area small.